1. Field of the Invention
This invention relates to a non-volatile semiconductor memory device, and more particularly to such a device function that detects a data state of an internal data hold circuit.
2. Description of Related Art
In a NAND-type flash memory, which is known as an EEPROM, data read or write is usually performed by a page, and this makes it possible to perform data write and read at a substantially high rate. Data erasure of the flash memory is usually performed by a block including plural pages, so that it is possible do data erase at a high rate.
Data write is performed, after having loaded one page write data into a data register (i.e., page buffer) in such a way that data are serially input byte by byte, by repeat of a write cycle including a write voltage application operation and the following verify-read operation until the entire data are written.
Usually, a positive threshold voltage state of a memory cell, which is a result of that electrons have been injected into the floating gate of the memory cell, is defined as a “0” data state. An operation for achieving this state is what is called a write operation in the narrow sense. A negative threshold voltage state of a memory cell, which is obtained by releasing electrons of the floating gate, is defined as a “1” data state. An operation for achieving this state is an erase operation in the narrow sense.
In every write cycle, write in the narrow sense (i.e., “0” data write) and write-inhibit (i.e., “1” data write) are controlled based on data “0” and “1”, respectively. When “0” write is verified as a result of verify-read, write data “0” held in the page buffer is inverted to “1”, and it becomes a write-inhibiting state hereinafter. Therefore, detect a state where all data is “1” in the page buffer, and it may be confirmed a write completion of one page.
In case data write is not completed in spite of that the number of write cycles has reached a predetermined maximum value (i.e., maximum write pulse application numbers) Nmax, the data write will be usually ended in “Fail”. However, if the judgment of whether the number of write cycles has reached the maximum value Nmax or not is done prior to the verify-read step, the result of Nmax detection should not always be ended in failure because there is a possibility that it has become “Pass” at the last write time.
To confirm that the entire page data have been written, or to detect how many faulty or defective bits (refer to as “fail bit” hereinafter), which have not be normally written, are there, it will be used a “fail bit count” method. This is such a method that the final verify-read is performed prior to ending the write sequence based on the detection that write cycle number has reached the maximum value, and then the resultant data held in the page buffer is read out to be subjected to fail bit number (i.e., “0” data bit number) counting.
However, since it is required of the conventional fail bit counting method to read the entire data in the page buffer, it takes a long time to do it. Explaining in detail, data in the page buffer are serially output to the input/output terminals byte by byte. Therefore, supposing that one page is constituted by N bytes, it is necessary for outputting the entire data in the page buffer to repeat the data output operation N times.
By contrast to this, there has been provided such a scheme that a fail bit counter circuit is prepared to be connected to the page buffer in the chip for counting fail bit numbers in a short time period (for example, refer to Unexamined Japanese Patent Application Publication No. 2002-140899).